A typical problem of electronic circuit design occurs in the design of an output driver stage when there is a need to regulate the current supplied to a load. This current limiting stage is necessary to protect the driving device from excessive currents due to a short-circuited condition at the output or other heavy load conditions that could lead to device overload failure.
Prior art current limiting circuits sample the current supplied to an output and then use the sampled current to regulate the current available to the output load. A common approach to the current sampling involves the use of a current mirror scheme. A typical prior art current mirror is shown in FIG. 1.
Transistor 12 in FIG. 1 is the output driving transistor. The current available at the output is primarily a function of the voltage at the base-emitter junction, Vbe12, and the physical characteristics of the device. The current flowing to the load at the output terminal is the collector current of 12, which may be expressed as: EQU Ic12=Is (1+Vce/Va)exp(Vbe/Vt)
The well known relationship between collector current, base-emitter voltage and collector-emitter voltage for a bipolar transistor is shown in FIG. 2. Note that the collector current depends primarily upon the Vbe voltage. In cases where the voltage Vce is low, the term Vce/Va may be quite small and almost ideal behavior occurs where the collector current is independent of the collector-emitter voltage. However, as Vce grows to large values the collector current begins to increase, independent of the voltage Vbe. This effect, the Early voltage effect, appears as increased gain and is often referred to as "beta modulation".
In the current mirror of prior art, as in FIG. 1, the transistor 18 is used to generate a reference current. It can be readily seen that if the two transistors are identical, then Is12=Is18, and as connected in FIG. 1 the base-emitter voltages Vbe12 and Vbe18 are equal as well. In this case Ic12=Ic18 so long as Vce12=Vce18.
However, the sampled current produced by the prior art current mirror may not reflect the output current accurately due to the conditions at the output. For example, if the output transistor saturates, the output current will fall, while the sampled current remains high, which may cause premature current limiting. Conversely, in a short-circuited situation the output current may increase rapidly while the sampled current remains stable, thus limiting may not occur as desired. As will be discussed herein, this is of particular importance in applications where low voltages do indeed occur at the output terminal of a driving circuit.